This invention relates generally to bias generator circuits and more particularly, it relates to a bias generator circuit which produces a first higher voltage for biasing a N-well region and a second delayed and lower voltage for biasing a source region of a P-channel field-effect transistor so as to increase latch-up immunity.
There is shown in FIG. 1 a cross-sectional view of a portion of an integrated circuit 10 containing a P-channel field-effect transistor (FET). The field-effect transistor is formed of a P-conductivity type regions 12 and 14 which are diffused in a N-conductivity type well 16. The N-well region 16 is formed in or on a P-conductivity type substrate 18. The P-type region 12 is defined to be the source electrode and the P-type region 14 is defined to be the drain electrode. The source and drain electrodes form the ends of a conduction channel. Overlying the space between the source and drain regions is an insulator layer 21 such as silicon dioxide over which is formed a gate electrode 22. Further, a N-type region 24 is also formed in the N-well region 16 in a laterally spaced apart relationship to the P-type region 14. The N-well region 16 and the P-type region 12 form a PN junction and are both tied to a common supply voltage or potential VCC.
In order to prevent the forward bias (referred to as CMOS SCR latch-up) of the PN junction between the diffused source region 12 and the N-well region 16, there has been attempted in the prior art of generating two separate supply voltages in which a first higher voltage VCC1 or V.sub.nw is used to bias the N-well region 16 and a second lower voltage VCC2 is used for biasing the source region 12 of the P-channel transistor. This arrangement is illustrated in FIG. 2 of the drawings. However, this arrangement suffers from the problem of a racing condition which exists between the higher voltage VCC1 applied to the N-well region and lower voltage VCC2 applied to the source region. Due to the resistivity of the N-well region 16 shown as resistors RW1 and RW2, the higher voltage VCC1 will have a larger RC time delay in reaching voltage point VW2 than the lower voltage VCC2. Thus, if the second voltage VCC2 is greater than the voltage VW2 by 0.65 volts, the PN junction would be forward bias, thereby still causing CMOS SCR latch-up to occur. The time delay of voltage VW2 relative to the first voltage VCC1 is depicted in FIG. 2(b).
The present invention provides a means of generating a first voltage for biasing a N-well region which is higher and occurs prior to a second voltage for biasing a source region of a P-channel transistor so as to insure preventing of latch-up from occurring during a power-up sequence. This is accomplished by the instant bias generator circuit which delays supplying of the second voltage until the first voltage has been pumped up to a level in excess of power supply voltage.